1. Technical Field
The embodiments described herein relate to a semiconductor memory apparatus and, more particularly, to a semiconductor memory apparatus including a sub-word line driver.
2. Related Art
In general, a dynamic random access memory (DRAM) is equipped with a large number of memory cells in which each memory cell includes a transistor and a capacitor for storing data. Each memory cell is connected to word lines and bit lines. If the word lines are activated, the memory cells can receive or output data to and from the bit lines. The word lines are classified into main word lines and sub-word lines. One main word line is connected to a plurality of preset sub-word line drivers (e.g., 8 sub-word line drivers), and each of the sub-word line drivers is connected to one sub-word line. The sub-word lines are directly connected to a plurality of memory cells.
A row decoder is provided at a memory cell area which decodes row addresses to generate main word line enable signals and sub-word line enable signals in order to selectively activate main word lines and the sub-word lines. When the main word line enable signal is enabled, a main word-line driver activates one of the main word lines. Thereafter, among a plurality of sub-word line drivers connected to the activated main word line, the sub-word line driver that has received an enabled sub-word line enable signal activates a corresponding sub-word line to support data input/output operations of corresponding memory cells.
The configuration of the sub word-line driver performing the above operation typically includes three transistors. In detail, the sub word-line driver includes a driving unit and a sink unit. The driving unit includes two transistors to activate a corresponding sub-word line in response to activation of a corresponding main word line and a corresponding sub-word line enable signal. The sink unit includes one transistor to drop the potential of the sub-word line to a low level in a pre-charge operation in response to the sub-word line enable signal that is inverted.
However, in this type of sub-word line driver, a memory core area having an extremely small area margin can result. Accordingly, this type of the sub-word line driver configuration that includes three transistors can result in occupying a relatively large area. If the occupation area of the sub-word line driver can be reduced, an area margin of the memory core area may be increased. Accordingly, the integration degree of the semiconductor memory apparatus may also be improved. However, the number of transistors cannot be reduced because a stable potential level is needed to prevent or minimize unwanted excessive noise levels in each of the sub-word lines. Therefore, it is difficult to improve the integration degree of a semiconductor memory apparatus if blocks and apparatuses are arranged in the memory core area as described above. Accordingly, new technologies or configurations are needed to increase an area margin in the memory core area.